The present invention is directed to semiconductor devices and, more specifically, to a thyristor memory device.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology may now permit single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second, to be packaged in relatively small semiconductor device packages. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store information. Conventional random access memory devices may include a variety of circuits, such as SRAM and DRAM circuits. SRAMS are mainly used in applications that require a high random access speed and/or a CMOS logic compatible process. DRAMS, on the other hand, are mainly used for high-density applications where the slow random access of DRAM can be tolerated.
Some SRAM cell designs may consist of at least two active elements, one of which may include an NDR (Negative Differential Resistance) device. Overall performance of this type of SRAM cell may be based in large part upon the properties of the NDR device. A variety of NDR devices have been introduced in various applications, which may include a simple bipolar transistor or a complicated quantum-effect device. One advantage of an NDR-based cell for an SRAM design may be its potential for allowing a cell area smaller than conventional SRAM cells (such as the 4T or 6T cells). Many of the typical NDR-based SRAM cells, however, may have deficiencies that may prohibit their use in some commercial SRAM applications. Some of these deficiencies may include: high power consumption due to the large standby current for its data retention states; excessively high or excessively low voltage levels for cell operation; and/or sensitivity to manufacturing variations which may degrade its noise immunity; limitations in access speed; limited operability over a given temperature range and limited yield due to a variety of fabrication tolerances.
Recently, thyristors have been introduced as a type of NDR device for forming a thyristor-based memory device. These types of memory can potentially provide the speed of conventional SRAM but with the density of DRAM and within a CMOS compatible process. Typically, such thyristor-based memory may comprise a capacitively coupled thyristor to form a bi-stable element for an SRAM cell. For more details and for more specific examples of such device, reference may be made to “Semiconductor Capacitively-Coupled NDR Device and its Applications in High-Density High-Speed Memories and in Power Switches,” U.S. patent application Ser. No. 09/092,449, now U.S. Pat. No. 6,229,161; issued May 8, 2001, hereby incorporated by reference in its entirety.
One consideration in the design of thyristor-based memories may be its cell area. The fabrication of a memory cell typically involves forming at least one storage element and circuitry designed to access the stored information. The cell area of a DRAM is typically between 6 F2 and 8F2, where F may be the minimum feature size.
Another consideration in the design of semiconductor memories may be the density of memory arrays. One factor in achieving a memory array of high density may be the ability to isolate the different circuitry components.
Another consideration in the design of semiconductor memories may be the cost of fabrication. One factor in the cost of memory fabrication may be the fabrication method.
Another consideration in the design of semiconductor memories may be the ability to reliably store data. For example, a thyristor-based memory may lose or corrupt data if it should accidentally turn-off (stored data may transition to ‘0’) or turn-on (stored data may transition to ‘1’).